Signals/Connections
Power Inputs:
PLL
V CCP
V CCQL
V CCQH
V CCA
V CCD
V CCC
4
3
3
4
2
Core Logic
I/O
Address Bus
Data Bus
Bus Control
DSP56311
Interrupt/Mode
Control
8
During Rese t
MODA
MODB
MODC
MODD
RESET
Non-Multiplexed
Bus
After Reset
IRQA
IRQB
IRQC
IRQD
RESET
Multiplexed
Bus
Port B
GPIO
V CCH
V CCS
GND P
GND P1
GND
2
64
HI08
ESSI/SCI/Timer
Grounds:
PLL
PLL
General
Host
Interface
(HI08) Port1
H[0–7]
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HAD[0–7]
HAS /HAS
HA8
HA9
HA10
Double DS
HRD/HRD
PB[0–7]
PB8
PB9
PB10
PB13
PB11
HDS/HDS
HWR/HWR
PB12
EXTAL
XTAL
Clock
Single HR
HREQ/HREQ
HACK/HACK
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
PB14
PB15
During
Reset
PINIT
PCAP
CLKOUT 4
After
Reset
NMI
PLL
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0) 2
3
SC0[0–2]
SCK0
SRD0
STD0
Port C GPIO
PC[0–2]
PC3
PC4
PC5
A[0–17]
D[0–23]
AA[0–3]/
RAS[0–3] 4
RD
WR
TA
18
24
4
Port A
External
Address Bus
External
Data Bus
External
Bus
Control
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1) 2
Serial
Communications
Interface (SCI) Port 2
3
SC1[0–2]
SCK1
SRD1
STD1
RXD
TXD
SCLK
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Port E GPIO
PE0
PE1
PE2
Timer GPIO
BR
BG
BB
CAS 4
BCLK 4
BCLK 4
Timers 3
JTAG/OnCE
Port
TIO0
TIO1
TIO2
TCK
TDI
TDO
TMS
TIO0
TIO1
TIO2
TRST
DE
2-2
Notes:
1.
2.
3.
4.
The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS/HAS) have configurable polarity.
The ESSI0, ESSI1, and SCI signals are multiplexed: ESSI0 with the Port C GPIO signals (PC[0–5]), ESSI1 with Port
D GPIO signals (PD[0–5]), and SCI with Port E GPIO signals (PE[0–2]).
TIO[0–2] can be configured as GPIO signals.
These signals are not supported above 100 MHz.
Figure 2-1. Signals Identified by Functional Group
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
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